Base element for a multiplexer structure and corresponding multiplexer structure

ABSTRACT

Basis element for a multiplexer structure and corresponding multiplexer structure.  
     Disclosed is a divided multiplexer structure which can be used to replace a tristate bus, comprising node elements ( 2 ) which are embodied in such a way that no feedback can occur in between the interconnected nodes ( 2 ). For this purpose, each node ( 2 ) is endowed with at least one feedback-free connection port (Bi, Bo).

[0001] The present invention relates to a base element according to thepreamble of claim 1, which can be used for constructing a multiplexerstructure, and a multiplexer structure comprising several such baseelements, which can be used in particular to replace a tristate bus.

[0002] A tristate bus is preferably used wherever data is exchangedbetween different periphery or data transmission and receiving units.Possible areas of application are thus, for example, computer or chiptechnology etc.

[0003] In many designs, the tristate bus is replaced by a cascadedmultiplexer structure, in which all bus or data signals of the coupleddata transmission and data receiving units must flow via the last stageof the cascade. A corresponding example is illustrated in FIG. 4. Asshown by FIG. 4, several data transmission and data receiving units 1designated below as “modules” for the sake of simplicity areinterconnected in a cascade way through logic OR gates 7. Each module 1has a data input IN, via which a corresponding module-specific datasignal can be supplied to the tristate bus or multiplexer structure. Forthis purpose, a logic AND gate 6 is illustrated in FIG. 4 for eachmodule 1, to which on the one hand the data input signal IN and on theother hand an enabling signal EN are supplied, whereby theinterconnection or output of the corresponding data signal IN can becontrolled by means of the enabling signal EN. All data signals of theconnected modules 1 must flow via the last stage of the illustratedcascade. This last stage then distributes all input signals IN of themultiplexer structure back to the inputs of the driving modules 1. Adisadvantage associated with this cascaded multiplexer structure is dueto the fact that all input signals IN must converge at a central pointin the circuit layout and be routed back from there to all coupledmodules 1 via buffer 8, which results in unfavourable load distribution.Thereby, a high unit density (“routing congestion”) occurs at thiscentral point in the circuit layout as well as the need for the buffers8 shown in FIG. 4, which together form a so-called “buffer tree”.

[0004] The underlying object of the present invention is to create abase element for an alternative multiplexer structure and a multiplexerstructure comprising several such base elements, which can be used toreplace a tristate bus, and avoids the disadvantages associated with theuse of a cascaded multiplexer structure, in particular unfavourable loaddistribution within the circuit.

[0005] This object is achieved according to the invention through a baseelement with the features of claim 1 or a multiplexer structurecomprising several base elements of this kind with the features of claim7. The sub-claims in each case define preferred and advantageousembodiments of the present invention.

[0006] According to the invention, a base or node element is proposed,which can be used to construct a divided multiplexer structure. Thisbase element includes several connection points, which in each casecomprise a signal input and a signal output. At the same time, the baseelement is embodied in such a way that at least one of these connectionpoints or ports is feedback-free and at least one other of theseconnection points has feedback, so that a further base or node elementcan be coupled to this connection point. This can be realized bysuitable logic circuit means, which ensure that at least one connectionpoint is feedback-free and at least one other connection point hasfeedback.

[0007] By means of such base or node elements, chains of similarlyconstructed nodes can be formed, to which again several data input anddata output units or modules can be coupled. The individual nodeelements are preferably embodied in such a way that each node outputalways drives the same number of data inputs, which results in veryfavourable load distribution. Also, favourable electrical features(smaller drivers, no short-term overloading due to overlapping) resultfrom this together with simple handling (homogeneously constructedelements, timing verification with standard methods) and favourablelayout behaviour (regular unit density). At the same time, connectionpoints, which do not need to be feedback-free, can be designed withfeedback, whereby the cost of the base element is reduced.

[0008] With the multiplexer structure according to the invention, it canbe further proposed that two base elements are interconnected so thateach base element is coupled to the other base element via a connectionpoint without feedback. In this way, two connection points withoutfeedback always lie between two base elements. Thus, it is possible toprevent feedbacks being formed over several base elements, which couldoccur under certain circumstances, if in each case only onefeedback-free input were to lie in between two interconnected baseelements.

[0009] The present invention is, in particular, suitable for chippackages with an on-chip tristate bus. Naturally, the present inventionis, however, also suitable for any other scope of application, where amultiplexer structure with several data transmission and data receivingunits (“modules”) could be used to replace a tristate bus.

[0010] The present invention is described in more detail below withreference to the attached drawing on the basis of preferential exemplaryembodiments.

[0011]FIG. 1 shows the structure and interconnection of base or nodeelements in accordance with a preferred exemplary embodiment of thepresent invention,

[0012]FIG. 2 shows a divided multiplexer structure composed of severalnode elements illustrated in FIG. 1 as replacement for a tristate bus inaccordance with a preferred exemplary embodiment of the presentinvention,

[0013]FIG. 3 shows the structure and interconnection of node elementswith feedback, and

[0014]FIG. 4 shows a cascaded multiplexer structure according to priorart.

[0015] Before dealing in greater detail with the exemplary embodimentsaccording to the invention shown in FIG. 1 and FIG. 2, first a nodestructure, which forms the basis of the present invention, but havingunwanted feedback at a connection point between two nodes will bedescribed with reference to FIG. 3.

[0016] As shown by FIG. 3, each node or base element 2 has fourconnection points or connection ports in each case with a signal inputAi, Bi, Ci, Di and a signal output Ao, Bo, Co, Do. Modules 1 in eachcase can be coupled to the individual connection ports, in the case ofwhich essentially data transmission and data receiving units areconcerned, which exchange data between one another via the node ormultiplexer structure illustrated. The nodes 2 are embodied in such away that a signal, which is received at a connection port is passed ontothe data outputs of all four connection ports. A simple structure of anode 2 can be realized by a quadruple OR gate. With the example shown inFIG. 3, however, a node 2 with a quadruple AND gate is realized, wherebythe connected modules 1 in a state of rest drive logic “1” to the bus.This is achieved due to the fact that each module 1 has a logic OR gate,to which on the one hand the corresponding data input signal IN and anenabling signal EN is supplied, whereby the enabling signal EN in eachcase is active on a low level. Only the module 1 active in each case canalso transmit a logic “0” to the bus.

[0017] As shown by FIG. 3, where nodes 2 constructed in this way arecoupled, a feedback loop illustrated with a dotted line in FIG. 3results, which is wanted at those connection ports, to which modules 1are coupled, in order to transmit the data input signal at a connectionport to a module 1 coupled to another connection port in the form of adata output signal. The disadvantage of the node structure shown in FIG.3, however, is that two nodes 2 cannot be interconnected due to thisfeedback, since the resulting bus does not function through the logicloop formed in this way, as also evident from the illustration of FIG. 3concerning the connection ports Bi, Bo of the left node 2 and theconnection ports Do, Di of the right node 2.

[0018] In FIG. 1, several interconnected nodes 2 according to thepresent invention are illustrated, whereby the problem described aboveis solved in such a way that each node 2 possesses a feedback-freeconnection port, to which a further node 2 can be coupled. Hereby, it ispossible to construct a network of nodes 2. In regard to theinterconnection of the nodes 2 to a divided bus or divided multiplexerstructure, it must be ensured that in each case at least onefeedback-free connection port always lies between two adjacent nodes 2and the modules 1 are coupled to connection ports with feedback. In FIG.1, the feedback-free connection ports of the nodes 2 in each case areshown with a broken line and in each case include the signal input Biand the signal output Bo. All other connection ports Ai, Ao, Ci, Co andDi, Do comprise a feedback.

[0019] With the embodiment illustrated in FIG. 1, the connection portsBi, Bo are feedback-free due to the fact that a quadruple AND gate 4 isproposed, to which the input signals of all connection ports aresupplied, whereby the output signal of this quadruple AND gate 4 is onlypassed onto the signal outputs Ao, Co, Do—not however to the signaloutput Bo. In addition, a logic triple AND gate 5 is proposed, theinputs of which are coupled to the signal inputs Ai, Ci, Di of theconnection ports with feedback, whereby the output signal of this logictriple AND gate 5 drives the signal output Bo of the connection portwithout feedback. In this way, it is ensured that no feedback occurs atthe connection point between two adjacent nodes 2, i.e. between theconnection ports Bi, Bo of the one node and the connection ports Do, Diof the other node.

[0020] As in the case for the structure illustrated in FIG. 3 also inregard to the embodiment according to the invention illustrated in FIG.1, the internal structure of the nodes 2 is realized by logic AND gates4, 5, so that the connected modules 1 in a state of rest must transmitlogic “1” to the bus. This is again realized by means of a logic OR gate3, which apart from the respective data input signal IN receives anenabling signal EN, that is active on a low level. In each case, onlythe active module 1 can also transmit a logic “0” to the bus.

[0021] Naturally, an equivalent circuit, in which the logic nodes 2 areconstructed with logic OR gates, can be realized. Likewise, naturallynodes 2 with more or fewer connection ports are also conceivable,whereby however it must always be ensured that at least one connectionport is feedback-free.

[0022] As mentioned above, a multiplexer structure with distributed load(“divided multiplexer structure”) can be formed by means of the nodes 2embodied according to the invention, whereby the disadvantages describedat the beginning are void, since chains can be realized from similarlyconstructed nodes 2, whereby each node output always drives the samenumber of inputs. In regard to the present embodiment, each node 2possesses four connection ports in each case with a data input and adata output, to which either further nodes 2 or modules 1 can becoupled. Since the operating time between the modules 1 depends on thenumber of nodes 2 connected in series, a correspondingly favourable nodetopology should be selected.

[0023]FIG. 2 shows an example of such a favourable node topology, whichcan be used to construct a divided multiplexer structure. The connectionports of the nodes 2, which are feedback-free, are again shown with abroken line in each case.

1. Base element for a multiplexer structure, with several connectionpoints which in each case comprise a signal input (Ai, Bi, Ci, Di) and asignal output (Ao, Bo, Co, Do) and with signal distribution means (4,5), which communicate with the individual signal inputs and signaloutputs, in order to pass on a signal at a signal input of a connectionpoint to at least one of the signal outputs, characterized in that thesignal distribution means (4, 5) are embodied in such a way that for atleast one particular connection point they prevent a signal at thesignal input (Bi) of this particular connection point being passed on tothe signal output (Bo) of the same particular connection point and thatfor at least another connection point they pass on a signal at thesignal input (Ai, Ci, Di) of this other connection point to the signaloutput (Ao, Co, Do) of the same other connection point.
 2. Base elementaccording to claim 1, characterized in that the signal distributionmeans (4, 5) are embodied in such a way that they pass on the signal atthe signal input (Bi) of the particular connection to the signal outputs(Ao, Co, Do) of all other connection points and a signal at a signalinput (Ai, Ci, Di) of another connection point to the signal output (Bo)of the particular connection point.
 3. Base element according to claim 1or 2, characterized in that the base element has four connection pointsin each case with a signal input (Ai, Bi, Ci, Di) and a signal output(Ao, Bo, Co, Do).
 4. Base element according to any one of the aboveclaims, characterized in that the signal distribution means include afirst logic circuit (4), which connects the signal inputs (Ai, Bi, Ci,Di) of all connection points with the signal outputs (Ao, Co, Do) ofthose connection points, which do not correspond to the particularconnection point.
 5. Base element according to one of the above claims,characterized in that the signal distribution means include a secondlogic circuit (5), which connects the signal inputs (Ai, Ci, Di) ofthose connection points, which do not correspond to the particularconnection point, with the signal output (Bo) of the particularconnection point.
 6. Base element according to claim 4 or 5,characterized in that the first logic circuit (4) and/or the secondlogic circuit (5) are a logic AND circuit or a logic OR circuit. 7.Multiplexer structure, with several base elements (2) and severaltransmission/receiving units (1) coupled to the base elements (2) forthe exchange of data between one another via the base elements (2),whereby each base element (2) has several connection points in each casewith a data input (Ai, Bi, Ci, Di) and a data output (Ao, Bo, Co, Do),whereby each base element (2) has data distribution means (4, 5)communicating with the individual data inputs and data outputs to passon a data signal at a data input of a connection point to at least oneof the data outputs, and whereby the data distribution means (4, 5) areembodied in such a way that for at least one particular connection pointthey prevent a data signal at the data input (Bi) of this particularconnection point being passed on to the data output (Bo) of the sameparticular connection point and that for at least another connectionpoint they pass on a signal at the signal input (Ai, Ci, Di) of thisother connection point to the signal output (Ao, Co, Do) of the sameother connection point.
 8. Multiplexer structure according to claim 7,characterized in that the base elements (2) are embodied according toany one of claims 1-6.
 9. Multiplexer structure according to claim 7 or8, characterized in that in each case two base elements (2) areinterconnected via at least one particular connection point (Bi, Bo).10. Multiplexer structure according to any one of claims 7-9,characterized in that a transmission/receiving unit (1) in each case iscoupled to a connection point of a base element (2), which does notcorrespond to the particular connection point (Bi, Bo).
 11. Multiplexerstructure according to any one of claims 7-10, characterized in that twoconnected base elements (2) are coupled with one another by means of aconnection point in each case, for which the data distribution means (4,5) prevent a data signal at the data input (Bi) of this connection pointbeing passed on to the data output (Bo) of this connection point.